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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-16310-1E
32-Bit Microcontroller
CMOS
FR30 Series
MB91F127/F128
s DESCRIPTION
This model, designed on the basis of 32-bit RISC CPU (FR30 series), is a standard single-chip micro controller with built-in I/O resources and bus control functions. The functions are suitable for built-in control that requires high-speed CPU processing. MB91F127 includes 256 Kbytes built-in flash memory and 14 Kbytes built-in RAM. MB91F128 includes 510 Kbytes built-in flash memory and 14 Kbytes built-in RAM. The specifications of the devices are best suited for applications requiring high-level CPU processing capabilities, such as navigation system, high-performance FAX, and printer controller.
s FEATURES
FR-CPU * 32-bit RISC (FR30), load/store architecture, 5-step pipeline * Operating frequency : Internal 25 MHz * General register : 32bit x 16 registers * 16-bit fixed-length instructions (primitives), 1 instruction/1 cycle * Instructions of memory-to-memory transfer, bit processing, and barrel shift : Instructions suitable for built-in control (Continued)
s PACKAGE
100 pin, Plastic LQFP
(FPT-100P-M05)
MB91F127/F128
* Function entry/exit instructions, multi load/store instruction for register data : High-level language compatible instructions * Register interlock functions : Simple description of assembler language * Branch instructions with delay slot : Reduced overhead on branching process * Built-in multiplier/ Supporting at instruction level Signed 32-bit multiplying : 5 cycles Signed 16-bit multiplying : 3 cycles * Interrupt (saving PC and PS) : 6 cycles, 16 priority levels
Bus interface * Maximum of 25 MHz internal operation rate * 25-bit address bus (32 MB space) * 16-bit address output, 8/16-bit data input/output * Basic bus cycle : 2-clock cycle * Chip selection outputs specifiable in a minimum of 64 Kbytes steps : 6 outputs * Automatic wait cycle : Specifiable flexibly from 0 cycle to 7 cycles for each area * Supporting time-division input/output interface for address/data (for area 1 only) * Unassigned data/address terminals are available as input/output ports * Supporting little endian mode (selecting one area from area 1 to area 5) DMAC (DMA controller) * 8 channels * Transfer factor : Interrupt request of built-in resources * Transfer sequence : Step transfer/Block transfer/Burst transfer/Consecutive transfer * Transfer data length : Selectable among 8 bits, 16 bits, and 32 bits * Pausing is allowed by interrupt request UART * 3 channels * Full-duplex double buffer * Data length : 7 to 9 bits (no parity), 6 to 8 bits (with parity) * Asynchronous (start-stop synchronization) or CLK synchronous communication is selectable * Multi processor mode * Built-in 16-bit timer (U-Timer) used as a baud-rate generator : Generates an arbitrary baud rate * External clock is available as a transfer clock * Error detection : parity, frame, and overrun A/D converter (sequential transducer) * 8/10-bit resolution, 8 channels * Sequential comparison and transducer : At 25 MHz, 5.2 s * Built-in sample and hold circuit * Conversion mode : Selectable among single conversion, scan conversion, and repeat conversion * Activation : Selectable among software, external trigger, and built-in timer Reload timer * 16-bit timer : 3 channels * Internal clock : 2-clock cycle resolution, selectable among 2/8/32 dividing and external clock
(Continued)
2
MB91F127/F128
(Continued)
Other interval timers * 16-bit timer : 3 channels (U-Timer) * PPG timer : 4 channels * 16-bit OCU : 4 channels, ICU : 4 channels, Free-run timer : 1 channel * Watchdog timer: 1 channel Flash memory 510 KB * 510 KB FLASH ROM: Read/Write/Erase is allowed with a same power Built- in RAM 14 KB * D-bus RAM 12 KB, C-bus RAM 2 KB Bit search module * Position of a first bit that changes between "1" and "0" is searched in one cycle, within an MSB of one word. Interrupt controller * External interrupt input : Normal interruptx6 (INT0 to INT5) * Internal interrupt factors : UART, DMAC, A/D, Reload timer, UTIMER, delay interrupt, PPG, ICU, and OCU * Priority levels are programmable (16 levels) Reset factors * Power-on reset/watchdog timer/software reset/external reset Low power consumption mode * Sleep/stop mode Clock control * Built-in PLL circuit, selectable among 1-multiplication, and 2-multiplication * Gearing function : Operation clock frequencies are freely and independently specifiable for CPU and peripherals. Gear clocks are selectable among 1/1, 1/2, 1/4, and 1/8 (or among 1/2, 1/4, 1/8, and 1/16). Upper limit of peripheral operations is 25 MHz. Others * Package : LQFP-100 * CMOS technology : 0.35 m * Power supply voltage : 3.3 V0.3 V
s SERIES CONFIGURATION
Model name Outline FLASH memory D-bus RAM C-bus RAM MB91F127 Quantity production 256 KB 12 KB 2 KB MB91F128 Quantity production 510 KB 12 KB 2 KB MB91FV129 Evaluation product 510 KB 16 KB 2 KB
3
MB91F127/F128
s PIN ASSIGNMENT
(TOP VIEW)
4
P21/D17 P22/D18 P23/D19 P24/D20 P25/D21 P26/D22 P27/D23 P30/D24 P31/D25 P32/D26 P33/D27 P34/D28 P35/D29 P36/D30 VSS P37/D31 P40/A00 VCC P41/A01 P42/A02 P43/A03 P44/A04 P45/A05 P46/A06 P47/A07
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PG5/OC1 PG6/OC2 PG7/OC3 VCC PA6/CLK PA5/CS5/SC1 PA4/CS4/SI1 PA3/CS3/SO1 PA2/CS2 PA1/CS1 PA0/CS0 P86/ALE HST RST VSS MD0 MD1 MD2 P80/RDY P81/BGRNT/IN0 P82/BRQ/IN1 P83/RD P84/WR0 P85/WR1 P20/D16
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
PG4/OC0 PG3/OCPA3 PG2/OCPA2 PG1/OCPA1 PG0/OCPA0 PE0/INT0 PE1/INT1 VCC X0 X1 VSS PE2/INT2 PE3/INT3 PE4/INT4/TCI1 PE5/INT5/SC0 PE6/SI0 PE7/SO0 PF3/SC2/ATG PF2/SO2 PF1/SI2 PF0/TCI0 PJ7/AN7 PJ6/AN6 PJ5/AN5 PJ4/AN4 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
PJ3/AN3 PJ2/AN2 PJ1/AN1 PJ0/AN0 AVSS/AVRL AVRH AVCC P70/A24/FRCK/TCI2 P67/A23/IN3 P66/A22/IN2 VSS P65/A21 P64/A20 P63/A19 P62/A18 P61/A17 P60/A16 P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/A10 P51/A09 P50/A08
(FPT-100P-M05)
MB91F127/F128
s PIN DESCRIPTION
Note that the numbers in the table are not pin numbers on a package. Input/output No. Pin name Description circuit type 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 D16/P20 D17/P21 D18/P22 D19/P23 D20/P24 D21/P25 D22/P26 D23/P27 D24/P30 D25/P31 D26/P32 D27/P33 D28/P34 D29/P35 D30/P36 D31/P37 A00/P40 A01/P41 A02/P42 A03/P43 A04/P44 A05/P45 A06/P46 A07/P47 A08/P50 A09/P51 A10/P52 A11/P53 A12/P54 A13/P55 A14/P56 A15/P57 A16/P60 A17/P61 A18/P62 A19/P63 A20/P64 A21/P65 A22/P66/IN2 A23/P67/IN3
D
Bit 16 through bit 23 of external data bus. The terminals are available as general I/O ports (P20 through P27) when external bus width is specified at 8 bits or in singlechip mode.
D
Bit 24 through bit 31 of external data bus. The terminals are available as general I/O ports (P30 through P37) when the terminals are not used.
D
Bit 00 through bit 15 of external address bus. The terminals are available as general I/O ports (P40 through P47 and P50 through P57) when the terminals are not used as address buses.
D
Bit 16 through bit 23 of external address bus. The terminals are available as general I/O ports (P60 through P67) when the terminals are not used as address busses. [IN2,IN3]: Input terminals of input capture. This function is active when input capture is operating.
(Continued)
5
MB91F127/F128
No.
Pin name
Input/output circuit type
Description Bit 24 of external address bus. [P70] A24, FRCK and TCI2 are available as general input ports when they are not used. [FRCK] External clock input of free-run timer. This function is active when external clock input of free-run timer is used. [TCI2] External clock input of timer 2. This function is active when external clock input of timer 2 is used. External ready input. Enter "0" when bus cycle under execution does not complete. This terminal is available as general input/ output port when it is not used. External bus open receive output. This terminal outputs "L" when an external bus is released. This terminal is available as general input/output port when it is not used. [IN0] Input capture input. This function is active when input capture is under input operation. External bus open request input. Enter "1" when releasing external bus. This terminal is available as general input/output port when it is not used. [IN1] Input capture input. This function is active when input capture is under input operation. External bus read strobe. This terminal is available as general input/output port when it is not used. External bus write strobe.Control signals and data bus byte positions are related as the following : 16-bit bus width D31 to D24 WR0 WR1 D23 to D16 8-bit bus width WR0 (port allowed) Single chip mode (port allowed) (port allowed)
41
A24/P70/FRCK/ TCI2
D
42
RDY/P80
D
43
BGRNT/P81/IN0
D
44
BRQ/P82/IN1
D
45 46
RD/P83 WR0/P84
D D
47
WR1/P85
D
Note : WR1 is set to Hi-z during resetting. For using with 16-bit bus width, use an external pull-up resistor. [P84 or P85] Available as general input/output ports when WR0 and WR1 are not used. 48 49 50 CS0/PA0 CS1/PA1 CS2/PA2 Chip select 0 output (Low active) Chip select 1 output (Low active) Chip select 2 output (Low active) [PA0,1,or 2] Available as general input/output ports when CS0, CS1 and CS2 are not used.
D
(Continued)
6
MB91F127/F128
No.
Pin name
Input/output circuit type
Description Chip select 3, 4, 5 output (Low active). [PA3,4,5] Available as general input/output ports when channel 1 of chip select UART is not used. [SO1,SI1,SC1] Data output, data input, and clock terminals of UART1. Active when UART1 operation is allowed. System clock output. Outputs a same clock as the same frequency of external bus operation. [PA6] Available as general input/output ports it is not used.
51 52 53
CS3/PA3/SO1 CS4/PA4/SI1 CS5/PA5/SC1
D
54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
CLK/PA6 OCPA0/PG0 OCPA1/PG1 OCPA2/PG2 OCPA3/PG3 OC0/PG4 OC1/PG5 OC2/PG6 OC3/PG7 MD0 MD1 MD2 X0 X1 RST HST P86/ALE INT0/PE0 INT1/PE1 INT2/PE2 INT3/PE3
D
D
[OCPA0 to 3] PPG timer outputs. The function is active when PPG timer output is allowed. [OC0 to 3] Output comparison output. The function is active when output comparison output is allowed. [PB0-7] Available as general input/output ports it is not used.
B
Mode terminals 0 through 2. The terminals specify basic operation mode of MCU. Use the terminals by connecting them directly to VCC or VSS. Clock (oscillation) input. Clock (oscillation) output. External reset input. Hardware standby input. [ALE] Address latch signal output. The function is active when ALE output of EPCR is allowed. [INT0,1,2,3] External interrupt request inputs. The input is used whenever necessary if external interrupt is allowed. Output of other functions must be suspended if not on purpose. [PE0,1,2,3] General input/output port [INT4,5] External interrupt request inputs.The input is used whenever necessary if concerned external interrupt is allowed. Output of other functions must be suspended if not on purpose. [TCI1] External clock input of timer 1. [SC0] Clock input of UART0. [PE4,5] General input/output port [SI0] Data input of UART0.This function is active when data input of UART0 is allowed. [PE6]General input/output port [SO0] Data output of UART0.This function is active when data output of UART0 is allowed. [PE7] General input/output port
A C C D
71 72
D
75 76
INT4/PE4/TCI1 INT5/PE5/SC0
D
77
SI0/PE6
D
78
SO0/PE7
D
(Continued)
7
MB91F127/F128
(Continued)
No. 79 Pin name PF0/TCI0 Input/output circuit type D Description [TCI0] External clock input of timer 0. [PF0] General input/output port [SI2] Data input of UART2.This function is active when data input of UART2 is allowed. [PF1] General input/output port [SO2] Data output of UART2.This function is active when data output of UART2 is allowed. [PF2] General input/output port. This function is active when data output of UART2 is disallowed. [SC2] Clock input of UART2 [ATG]External trigger input of A/D converter The input is used whenever necessary if a function concerned is selected. Output of other functions must be suspended if not on purpose. [PF3] General input/output port AN0/PJ0 AN1/PJ1 AN2/PJ2 AN3/PJ3 AN4/PJ4 AN5/PJ5 AN6/PJ6 AN7/PJ7 AVCC AVRH [AN0 to AN7] Analog input of A/D converter. This function is active when analog input is specified in AIC register. E [PJ0 through PJ7] General input/output ports
80
SI2/PF1
D
81
SO2/PF2
D
82
SC2/PF3/ATG
D
83 to 90
91 92

VCC power supply for A/D converter Reference voltage of A/D converter (high potential side). Be sure to turn on or off this terminal with a potential higher than AVRH applied to VCC. A/D converter VSS power source and reference voltage (low potential side). Power sources of digital circuits. Be sure to connect power source to all terminals when the device is used. Ground level of digital circuits.
93 94 to 96 97 to 100
AVSS/AVRL VCC VSS
Note : Most of the above terminals multiplex inputs and outputs of I/O ports and resources, as indicated as "XXXX/ PXX". If the outputs of ports and resources conflict with each other on the terminals, resources take preferences.
8
MB91F127/F128
s INPUT/OUTPUT CIRCUIT TYPE
Type
X1
Circuit
Clock input
Remarks * For 25 MHz system * Oscillation feedback register : Approx. 1M * Standby control is available.
A
X0 STANDBY
* CMOS level input * High-voltage control is available for FLASH test. B
Control signal Mode input Diffused resistor
P-channel transistor
* CMOS level hysteresis input * Standby control is not available.
C
N-channel transistor Diffused resistor Digital input CMOS
Digital output
* CMOS level output * CMOS level hysteresis input * Standby control is available
D
Diffused resistor
Digital output
STANDBY
Digital input
Digital output
* * * *
Standby control is available CMOS level output CMOS level hysteresis input Analog input
E
Diffused resistor
Digital output
Analog input STANDBY Digital input
9
MB91F127/F128
s HANDLING DEVICES
1. Preventing latch up
On a CMOS IC, latch up may occur when a voltage higher than VCC or a voltage lower than VSS is applied to input terminal or output terminal, or when a voltage exceeding rated level is applied across VCC and VSS. Latch up causes drastic increase of power source current, which may result in destruction of the element by heat. Take extra care not to exceed maximum rating in use. Also, take extra care so that analog terminal does not exceed digital power source.
2. Treatment of unused input terminals
Leaving unused terminals open may cause malfunction. Apply pull-up or pull-down treatment on unused terminals.
3. External reset input
Complete resetting of internal system requires inputting "L" level signal to RST terminal for a minimum of 5 machine cycles.
4. Notes on using external clock
When using an external clock, supply a clock signal to X0 terminal and supply its antiphase clock to X1 terminal simultaneously. In this case, do not use STOP mode (oscillation stop mode). (Because X1 terminal halts with "H" output under STOP status.) Under a 12.5 MHz frequency, the device operates with a clock supplied to X0 terminal only. Figures show examples of using an external clock. Example of using external clock (normal)
X0 X1
Note : STOP mode (oscillation stop mode) is not available. Example of using external clock (allowed under operation at 12.5 MHz or lower frequency)
X0 OPEN X1
10
MB91F127/F128
5. Connecting power supply terminals (VCC, VSS)
If two or more VCC, VSS terminals are used, the terminals to be placed under the same potentials are connected with each other internally for preventing malfunctions such as latch up. However, for reducing unwanted radiation, preventing malfunctions of strobe signals and observing total power and current ratings, be sure to connect all of these terminals to power supply and ground externally. Connecting power supply to VCC - VSS in impedance as low as possible is desirable.
6. Crystal oscillator circuit
Noises around X0 and X1 terminals causes malfunction of the device. Design printed wiring so that X0, X1, and crystal oscillator (or ceramic oscillator), and bypass capacitor to the ground are aligned as close as possible one another. Also the wiring of those elements should not cross with other wiring if possible. Printed wiring with ground wires around X0 and X1 terminals ensures more stable operations. Such designing is strongly recommended.
7. Treating NC terminals
Be sure to leave NC terminals open.
8. Mode terminals (MD0 through MD2)
Do not connect the mode terminals directly to VCC or VSS. For preventing malfunctions caused by noises, make printed traces between the mode terminals and VCC or VSS as short as possible, and connect the elements in lower impedance.
9. Turning power on
Be sure to turn on the power of the device with RST terminal placed under "L" level. Ensure a period at a minimum of 5 cycles of internal operation clock before placing the terminal under "H" level.
10. Terminal status upon turning on power
Status upon turning on the power is indefinite. Upon turning on the power, oscillation starts and the circuit is initialized.
11. Oscillation input upon turning on power
Upon turning on the power, be sure to input a clock signal until oscillation stabilizing wait status is released.
12. Initializing power-on reset
The device includes some built-in registers that are initialized only with power-on reset operation. For initializing the registers, perform power-on reset by turning on the power again.
13. Recovery from Sleep/Stop status
For recovering from Sleep/Stop status initiated by a program in C-Bus RAM, reset the device instead of recovering by an interrupt process.
11
MB91F127/F128
s BLOCK DIAGRAM
FR CPU D-bus (32 bits) I-bus (16 bits)
RAM (12 Kbytes) Bit search module DMA controller (8 ch.)
Bus converter (Harvard - Princeton)
Bus converter (32 bits - 16 bits) X0 X1 RST HST INT0 to INT5 AN0 to AN7 AVCC AVSS/AVRL AVRH ATG 6 Interrupt control unit 8 10-bit A/D converter (8 ch.) R-bus (16 bits) Bus controller C-bus (32 bits)
16 25 2
Clock control unit (Watchdog timer)
6
D16 to D31 A00 to A24 RD WR0, WR1 RDY CLK BRQ BGRNT CS0 to CS5 ALE
SI0 to SI2 SO0 to SO2 SC0 to SC2 3
3 3 3
UART (3 ch)
Port2, 3, 4, 5, 6, 7, 8, A
TCI0 to TCI2
Reload timer (3 ch) 4 PPG
RAM (2 Kbytes)
OCPA0 to OCPA3 OC0 to OC3 IN0 to IN3 FRCK 4 4
ICU, OCU Free run timer Port E, F, G, J
Flash memory MB91F127:256 KB MB91F128:510 KB
Notes : * Terminals are described in functional groups (actual terminals are partially multiplexed). * For using REALOS, perform time management by external interrupt or built-in timer.
12
MB91F127/F128
s CPU CORE MEMORY SPACE
* MB91F127
External ROM External bus mode
0000 0000H I/O 0000 0400H I/O 0000 0800H
Internal ROM External bus mode
I/O
Single-chip mode Direct addressing areas I/O map
I/O
I/O
I/O
Access inhibit
0000 1000H
Access inhibit Internal RAM 12 KB
Access inhibit Internal RAM 12 KB
Internal RAM 12 KB
0000 4000H
Access inhibit
0001 0000H
Access inhibit
Access inhibit
0001 0000H
External area Internal RAM 2 KB External area Access inhibit
Access inhibit
0008 0000H
Internal RAM 2 KB
0008 0800H
Access inhibit
000C 0000H
FLASH ROM 256 KB
FLASH ROM 256 KB 0010 0000H
External area
FFFF FFFFH
Access inhibit
FFFF FFFFH
Note : External area is not accessible in single-chip mode. When accessing to external areas, select the internal ROM external bus mode in mode register. Direct addressing areas The areas described below are used for I/O processes. The areas, referred to as "direct addressing areas," allow specifying an operand address directly by an instruction. The direct addressing areas varies as the following, depending on size of the data to be accessed. * Byte-data access : 0 to 0FFH * Half-word data access : 0 to 1FFH * Word-data access : 0 to 3FFH
13
MB91F127/F128
* MB91F128
External ROM External bus mode
0000 0000H I/O 0000 0400H I/O 0000 0800H
Internal ROM External bus mode
I/O
Single-chip mode Direct addressing areas I/O map
I/O
I/O
I/O
Access inhibit
0000 1000H
Access inhibit Internal RAM 12 KB
Access inhibit Internal RAM 12 KB
Internal RAM 12 KB
0000 4000H
Access inhibit
0001 0000H
Access inhibit
Access inhibit
0001 0000H
External area Internal RAM 2 KB External area
FLASH ROM 510 KB
Access inhibit
0008 0000H
Internal RAM 2 KB
0008 0800H
FLASH ROM 510 KB
0010 0000H
External area
FFFF FFFFH
Access inhibit
FFFF FFFFH
Note : External area is not accessible in single-chip mode. When accessing to external areas, select the internal ROM external bus mode in mode register. Direct addressing areas The areas described below are used for I/O processes. The areas, referred to as "direct addressing areas," allow specifying an operand address directly by an instruction. The direct addressing areas varies as the following, depending on size of the data to be accessed. * Byte-data access : 0 to 0FFH * Half-word data access : 0 to 1FFH * Word-data access : 0 to 3FFH
14
MB91F127/F128
s LEGEND OF I/O MAP
address
000000H
Register +0
PDR3 [R/W] XXXXXXXX
+1
PDR2 [R/W] XXXXXXXX
+2
--------
+3
--------
Internal resource
Port Data Register
Read/write attribute Initial register value after reset Register name (the register listed in the first column is at address 4n, the register listed in the second column is at address 4n + 1, - - - ) Leftmost register address (the first column register is on the MSB side of data in word access mode)
Note : Register bit values indicate initial values as shown below : "1" : Initial value"1" "0" : Initial value"0" "X" : Initial value "X" "-" : Register does not exist physically in this position.
15
MB91F127/F128
s I/O MAP
Address 000000H 000004H 000008H 00000CH 000010H 000014H 000018H 00001CH 000020H 000024H 000028H 00002CH 000030H 000034H 000038H 00003CH 000040H 000044H 000048H 00004CH PDRG [R/W] XXXXXXXX SSR [R/W] 00001- 00 SSR [R/W] 00001- 00 SSR [R/W] 00001- 00 SIDR [R/W] XXXXXXXX SIDR [R/W] XXXXXXXX SIDR [R/W] XXXXXXXX Register +0 PDR3 [R/W] XXXXXXXX PDR7 [R/W] -------X +1 PDR2 [R/W] XXXXXXXX PDR6 [R/W] XXXXXXXX PDRA [R/W] XXXXXXXX PDRE [R/W] XXXXXXXX SCR [R/W] 00000100 SCR [R/W] 00000100 SCR [R/W] 00000100 PDRF [R/W] XXXXXXXX PDRJ [R/W] XXXXXXXX SMR [R/W] 00 - - 0 - 00 SMR [R/W] 00 - - 0 - 00 SMR [R/W] 00 - - 0 - 00 Reserved UART0 UART1 UART2 +2 PDR5 [R/W] XXXXXXXX +3 PDR4 [R/W] XXXXXXXX PDR8[R/W] - - XXXXXX Port data Register Internal resource
TMRLR [W] XXXXXXXX XXXXXXXX TMRLR [W] XXXXXXXX XXXXXXXX TMRLR [W] XXXXXXXX XXXXXXXX IPCP1[R] XXXXXXXX XXXXXXXX IPCP3[R] XXXXXXXX XXXXXXXX ICS23[R/W] 00000000
TMR [W] XXXXXXXX XXXXXXXX TMCSR [R/W] - - - - 0000 00000000 TMR [W] XXXXXXXX XXXXXXXX TMCSR [R/W] - - - - 0000 00000000 TMR [W] XXXXXXXX XXXXXXXX TMCSR [R/W] - - - - 0000 00000000 IPCP0[R] XXXXXXXX XXXXXXXX IPCP2[R] XXXXXXXX XXXXXXXX ICS01[R/W] 00000000
Reload Timer 0
Reload Timer 1
Reserved
Reload Timer 2
16 bit ICU
000050H
ADCR [W] 00101-XX XXXXXXXX
ADCS [R/W] 000000000 00000000
A/D converter (Serially compared)
(Continued)
16
MB91F127/F128
Address 000054H 000058H 00005CH 000060H 000064H 000068H 00006CH 000070H 000074H 000078H 00007CH 000080H 000084H 000088H 00008CH 000090H 000094H 000098H
Register +0 +1 +2 +3 OCCP1[R/W] XXXXXXXX XXXXXXXX OCCP3[R/W] XXXXXXXX XXXXXXXX OCS2, 3[R/W] XXX00000 0000XX00 TCDT [R/W] 00000000 00000000 UTM/UTIMR [R/W] 00000000 00000000 UTM/UTIMR [R/W] 00000000 00000000 UTM/UTIMR [R/W] 00000000 00000000 EIRR [R/W] 00000000 EHVR [R/W] - - - - 0000 ENIR [R/W] 00000000 ELVR [R/W] 00000000 OCCP0[R/W] XXXXXXXX XXXXXXXX OCCP2[R/W] XXXXXXXX XXXXXXXX OCS0, 1[R/W] XXX00000 0000XX00 TCCS [R/W] 0 - - - - - - - 00000000 UTIMC[R/W] 0 - - 00001 UTIMC[R/W] 0 - - 00001 UTIMC[R/W] 0 - - 00001
Internal resource
16 bit OCU
Reserved 16 bit OCU Reserved Free run timer Reserved Reserved U-Timer0 U-Timer1 U-Timer2 Reserved Reserved
External interrupt/ NMI
(Continued)
17
MB91F127/F128
Address 00009CH 0000A0H 0000A4H 0000A8H 0000ACH 0000B0H 0000B4H 0000B8H 0000BCH 0000C0H 0000C4H 0000C8H 0000CCH 0000D0H 0000D4H 0000D8H 0000DCH 0000E0H 0000E4H 0000E8H 0000ECH 0000F0H 0000F4H 0000F8H 0000FCH
Register +0 +1 DDRG [W] 00000000 AIC3[W] 11111111 DDRE [W] 00000000 -------DDRF [W] 00000000 DDRJ [W] 00000000 GCN2[R/W] 00000000 +2 +3
Internal resource
Reserved
Port direction register A/D converter Port direction register PPG ctl
GCN1 [R/W] 00110010 00010000 PTMR0 [R] 11111111 11111111 PDUT0 [W] XXXXXXXX XXXXXXXX PTMR1 [R] 11111111 11111111 PDUT1 [W] XXXXXXXX XXXXXXXX PTMR2 [R] 11111111 11111111 PDUT2 [W] XXXXXXXX XXXXXXXX PTMR3 [R] 11111111 11111111 PDUT3 [W] XXXXXXXX XXXXXXXX
PCSR0 [W] XXXXXXXX XXXXXXXX PCNH0[R/W] 0000000 PCNL0[R/W] 00000000
PPG0
PCSR1 [W] XXXXXXXX XXXXXXXX PCNH1[R/W] 0000000 PCNL1[R/W] 00000000
PPG1
PCSR2 [W] XXXXXXXX XXXXXXXX PCNH2[R/W] 0000000 PCNL2[R/W] 00000000
PPG2
PCSR3 [W] XXXXXXXX XXXXXXXX PCNH3[R/W] 0000000 PCNL3[R/W] 00000000
PPG3
(Continued)
18
MB91F127/F128
Address 000100H to 0001FCH 000200H 000204H 000208H 00020CH 000210H to 0002FCH 000300H to 0003ECH 0003F0H 0003F4 H 0003F8H 0003FCH
Register +0 +1 DPDP [R/W] - - - - - - - - - - - - - - - - - - - - - - - - -0000000 DACSR [R/W] 00000000 00000000 00000000 00000000 DATCR [R/W] - - - - - - - - - - XX0000 - - XX0000 - - XX0000 +2 +3
Internal resource
Reserved
DMAC
Reserved
BSD0 [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSDC [W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSRR [R/W] XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reserved
Bit search module
(Continued)
19
MB91F127/F128
Address 000400H 000404H 000408H 00040CH 000410H 000414H 000418H 00041CH 000420H 000424H 000428H 00042CH 000430H 000434H to 00047CH 000480H
Register +0 ICR00 [R/W] - - -11111 ICR04[R/W] - - -11111 ICR08 [R/W] - - -11111 ICR12[R/W] - - -11111 ICR16[R/W] - - -11111 ICR20[R/W] - - -11111 ICR24 [R/W] - - -11111 ICR28[R/W] - - -11111 ICR32[R/W] - - -11111 ICR36[R/W] - - -11111 ICR40[R/W] - - -11111 ICR44[R/W] - - -11111 DICR [R/W] -------0 +1 ICR01[R/W] - - -11111 ICR05[R/W] - - -11111 ICR09[R/W] - - -11111 ICR13[R/W] - - -11111 ICR17[R/W] - - -11111 ICR21[R/W] - - -11111 ICR25[R/W] - - -11111 ICR29[R/W] - - -11111 ICR33[R/W] - - -11111 ICR37[R/W] - - -11111 ICR41[R/W] - - -11111 ICR45[R/W] - - -11111 HRCL [R/W] - - -11111 RSRR/WTCR [R/W] 1XXXX - 00 GCR [R/W] 110011 - 1 PTCR [R/W] 00 - - 0 - - STCR [R/W] 000111- WPR [W] XXXXXXXX PDDR [R/W] - - - - 0000 CTBR [W] XXXXXXXX +2 ICR02[R/W] - - -11111 ICR06[R/W] - - -11111 ICR10[R/W] - - -11111 ICR14[R/W] - - -11111 ICR18[R/W] - - -11111 ICR22[R/W] - - -11111 ICR26[R/W] - - -11111 ICR30[R/W] - - -11111 ICR34[R/W] - - -11111 ICR38[R/W] - - -11111 ICR42[R/W] - - -11111 ICR46[R/W] - - -11111 +3 ICR03[R/W] - - -11111 ICR07[R/W] - - -11111 ICR11[R/W] - - -11111 ICR15[R/W] - - -11111 ICR19[R/W] - - -11111 ICR23[R/W] - - -11111 ICR27[R/W] - - -11111 ICR31[R/W] - - -11111 ICR35[R/W] - - -11111 ICR39[R/W] - - -11111 ICR43[R/W] - - -11111 ICR47[R/W] - - -11111
Internal resource
Interrupt controller
Delay interrupt
Reserved
Clock controller block
000484H 000488H 00048CH to 0005FCH
PLL controller block Reserved
(Continued)
20
MB91F127/F128
(Continued)
Address 000600H 000604H 000608H 00060CH 000610H 000614H 000618H 00061CH 000620H 000624H 000628H 00062CH 000630H to 0007BCH 0007C0H 0007C4H to 0007F8H 0007FCH FSTR [R/W] 000XXXX0 LER [W] - - - - - 000 MODR [W] XXXXXXXX Register +0 DDR3 [W] 00000000 DDR7 [W] -------0 +1 DDR2 [W] 00000000 DDR6 [W] 00000000 DDRA [W] -0000000 +2 DDR5 [W] 00000000 +3 DDR4 [W] 00000000 DDR8 [W] - - 000000 Data direction register Internal resource
ASR1 [W] 00000000 00000001 ASR2 [W] 00000000 00000010 ASR3 [W] 00000000 00000011 ASR4 [W] 00000000 00000100 ASR5 [W] 00000000 00000101 AMD0 [R/W] - - - XX111 AMD5[R/W] 0 - - 00000 AMD1 [R/W] 0 - - 00000 DSCR [W] 00000000
AMR1 [W] 00000000 00000000 AMR2 [W] 00000000 00000000 AMR3 [W] 00000000 00000000 AMR4 [W] 00000000 00000000 AMR5 [W] 00000000 00000000 AMD32[R/W] 00000000 AMD4 [R/W] 0 - - 00000 External bus interface
RFCR [R/W] --XXXXXX 00 - - - 000 EPCR1 [W] - - - - - - - 1 11111111 DMCR5 [R/W] 00000000 0000000 Reserved
EPCR0 [W] - - 1 - 1100 -1111111 DMCR4 [R/W] 00000000 0000000-
Flash memory
Reserved Little endian register mode register
Note : Do not issue RMW instructions to a register with write-only bit. RMW instructions (RMW : Read modify write) AND Rj, @Ri OR Rj, @Ri EOR Rj, @Ri ANDH Rj, @Ri ORH Rj, @Ri EORH Rj, @Ri ANDB Rj, @Ri ORB Rj, @Ri EORB Rj, @Ri BANDL #u4, @Ri BORL #u4, @Ri BEORL #u4, @Ri BANDH #u4, @Ri BORH #u4, @Ri BEORH #u4, @Ri Data in "Reserved" or "-" area is indefinite. 21
MB91F127/F128
s INTERRUPT CAUSES, INTERRUPT VECTORS AND INTERRUPT CONTROL REGISTER ALLOCATIONS
Interrupt causes Reset Reserved by system Reserved by system Reserved by system Reserved by system Reserved by system Reserved by system Reserved by system Reserved by system Reserved by system Reserved by system Reserved by system Reserved by system Reserved by system Undefined instruction exception NMI request External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 UART 0 reception complete UART 1 reception complete UART 2 reception complete UART 0 transmission complete UART 1 transmission complete UART 2 transmission complete Interrupt number
Decimal
Interrupt level Offset 3FCH 3F8H 3F4H 3F0H 3ECH 3E8H 3E4H 3E0H 3DCH 3D8H 3D4H 3D0H 3CCH 3C8H 3C4H 3C0H 3BCH 3B8H 3B4H 3B0H 3ACH 3A8H 3A4H 3A0H 39CH 398H 15 (FH) fixed ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09
Hexadecimal Register*1
TBR default Address*2 000FFFFCH 000FFFF8H 000FFFF4H 000FFFF0H 000FFFECH 000FFFE8H 000FFFE4H 000FFFE0H 000FFFDCH 000FFFD8H 000FFFD4H 000FFFD0H 000FFFCCH 000FFFC8H 000FFFC4H 000FFFC0H 000FFFBCH 000FFFB8H 000FFFB4H 000FFFB0H 000FFFACH 000FFFA8H 000FFFA4H 000FFFA0H 000FFF9CH 000FFF98H (Continued)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19
22
MB91F127/F128
Interrupt causes DMAC 0 (end, error) DMAC 1 (end, erro) DMAC 2 (end, erro) DMAC 3 (end, erro) DMAC 4 (end, erro) DMAC 5 (end, erro) DMAC 6 (end, erro) DMAC 7 (end, erro) A/D (sequential type) Reload timer 0 Reload timer 1 Reload timer 2 External interrupt 4 External interrupt 5 Reserved by system Reserved by system U-TIMER 0 U-TIMER 1 U-TIMER 2 FLASH memory Reserved by system Reserved by system PPG0 PPG1 PPG2 PPG3 ICU0 (capture) ICU1 (capture) ICU2 (capture) ICU3 (capture)
Interrupt number
Decimal Hexadecimal
Interrupt level Register*1 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 ICR16 ICR17 ICR18 ICR19 ICR20 ICR21 ICR22 ICR23 ICR24 ICR25 ICR26 ICR27 ICR28 ICR29 ICR30 ICR31 ICR32 ICR33 ICR34 ICR35 ICR36 ICR37 ICR38 ICR39 Offset 394H 390H 38CH 388H 384H 380H 37CH 378H 374H 370H 36CH 368H 364H 360H 35CH 358H 354H 350H 34CH 348H 344H 340H 33CH 338H 334H 330H 32CH 328H 324H 320H
TBR default Address*2 000FFF94H 000FFF90H 000FFF8CH 000FFF88H 000FFF84H 000FFF80H 000FFF7CH 000FFF78H 000FFF74H 000FFF70H 000FFF6CH 000FFF68H 000FFF64H 000FFF60H 000FFF5CH 000FFF58H 000FFF54H 000FFF50H 000FFF4CH 000FFF48H 000FFF44H 000FFF40H 000FFF3CH 000FFF38H 000FFF34H 000FFF30H 000FFF2CH 000FFF28H 000FFF24H 000FFF20H
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37
(Continued)
23
MB91F127/F128
(Continued)
Interrupt causes OCU0 (match) OCU1 (match) OCU2 (match) OCU3 (match) Reserved by system 16 bit free-run timer Reserved by system Delay interrupt cause bit Reserved by system (used by REALOS) *3 Reserved by system (used by REALOS) *3 Used by INT Interrupt number
Decimal
Interrupt level Offset 31CH 318H 314H 310H 30CH 308H 304H 300H 2FCH 2F8H 2F4H to 000H
Hexadecimal Register*1
TBR default Address*2 000FFF1CH 000FFF18H 000FFF14H 000FFF10H 000FFF0CH 000FFF08H 000FFF04H 000FFF00H 000FFEFCH 000FFEF8H 000FFEF4H to 000FFC00H
56 57 58 59 60 61 62 63 64 65 66 to 255
38 39 3A 3B 3C 3D 3E 3F 40 41 42 to FF
ICR40 ICR41 ICR42 ICR43 ICR44 ICR45 ICR46 ICR47
*1 : ICR specifies interrupt levels for interrupt requests, using the registers in interrupt controller. ICR is provided for each interrupt request. *2 : TBR is a register that indicates a head address of the vector table for EIT. An address that is found by adding offset values defined by TBR and EIT cause, is a vector address. *3 : If REALOS/FR is used, 0x40 and 0x41 interrupts are used for system code. Information : An 1 Kbyte area starting with an address indicated by TBR is the vector area for EIT. Size of the area for one vector is 4 byte. Relation between a vector number and a vector address is as follows: vctadr = TBR + vctofs = TBR + ( 3FCH - 4 x vct) Vctadr Vector address, vctofs: Vector offset, vct: Vector number
24
MB91F127/F128
s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Rating Min VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 VSS - 0.3 - 2.0 -30 -55 Max VSS + 4.0 VSS + 4.0 VSS + 4.0 VCC + 0.3 AVCC + 0.3 VCC + 0.3 + 2.0 20 10 4 100 50 -10 -4 -50 -20 500 +70 +150 (VSS = AVSS = 0 V) Symbol VCC AVCC AVRH VI VIA VO ICLAMP | ICLAMP | IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV Pd TA Tstg Unit V V V V V V mA mA mA mA mA mA mA mA mA mA mW C C *4 *4 *2 *3 *5 *5 *2 *3 *1 *1 Remarks
Parameter Power supply voltage Analog supply voltage Analog reference voltage Input voltage Analog input voltage Output voltage Maximum clamp current Total maximum clamp current "L" level maximum output current "L" level average output current "L" level maximum total output current "L" level average total output current "H" level maximum output current "H" level average output current "H" level maximum total output current "H" level average total output current Power consumption Operating temperature Storage temperature
*1 : Care must be taken that AVCC, AVRH do not exceed VCC + 0.3 V. Also, care must be taken that AVRH do not exceed AVCC. *2 : Maximum output current defines a peak value of a specific terminal. *3 : Average output current defines a mean value of current flow within a period of 100 ms in a specific terminal. *4 : Average total output current defines a mean value of current flow within a period of 100 ms in all terminals. *5 : * Aplicable to pins : D16 to D31, A00 to A24, RDY, BGRNT, BRQ, RD, WR0, WR1, CS0 to CS5, CLK, OCPA0 to OCPA3, OC0 to OC3, ALE, INT0 to INT5, SI0, SI2, SO0, SO2, TCI0, SC2 * Use within recommended operating conditions. * Use at DC voltage (current) . * The +B signal should always be applied with a limiting resistance placed between the +B signal and the microcontroller.
(Continued)
25
MB91F127/F128
(Continued)
* The value of the limiting resistance should be set so that when the signal is applied the input current to the microcontroller pins does not exceed rated values, either instantaneously or for prolonged periods. * Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices. * Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result. * Note that if the +B input is applied during power-on, the power suplly is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. * Care must be taken not to leave the input pin open. * Sample recommended circuits
* Input/Output equivalent circuits
Protective diode
VCC
Limiting resistance +B input (0 V to 16 V)
P-ch
N-ch
R
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
26
MB91F127/F128
2. Recommended Operating Conditions
Value Min 3.0 Power supply Analog supply voltage Analog reference voltage Operating temperature VCC AvCC AVRH TA 2.0 VSS - 0.3 AVSS -30 Max 3.6 3.6 VSS + 3.6 AVCC +70 V V V C
(VSS = AVSS = 0 V) Unit Remarks Normal operation Retain RAM data under "stop" condition
Parameter
Symbol
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
27
MB91F127/F128
3. DC Characteristics
(AVCC = VCC = 3.3 V 0.3 V, AVSS = VSS = 0 V, TA = -30 C to +70 C) Pin name Hysteresis input terminal Hysteresis input terminal Port2 to PortJ Port2 to PortJ Port2 to PortJ Condition VCC = 3.3 V IOH = -4.0 mA VCC = 3.3 V IOL = 4.0 mA VCC = 3.6 V VSS < VI < VCC 25 MHz VCC = 3.3 V 25 MHz VCC = 3.3 V 25 MHz VCC = 3.3 V TA = 25 C VCC = 3.3 V Other than AVCC, AVSS, AVRH, VCC, VSS Value Min 0.8 x VCC VSS-0.3 VCC-0.5 Typ 75 85 60 10 Max VCC + 0.3 0.2 x VCC 0.4 5 100 120 85 150 Unit Remarks V V V V A mA mA mA A FLASH writing Sleeping Stopping * *
Parameter "H" level input voltage "L" level input voltage "H" level output voltage "L" level output voltage Input leak current
Symbol
VIHS VILS VOH VOL ILI ICC ICC
Power supply current
VCC ICCS ICCH
Input capacity
CIN
10
pF
* : Refer to "s INPUT/OUTPUT CIRCUIT TYPE".
28
MB91F127/F128
4. AC Characteristics
(1) Clock Timing Ratings (VCC = 3.3 V 0.3 V, AVSS = VSS = 0 V, TA = -30 C to +70 C) Symbol
Condition
Parameter Clock frequency (High speed, automatic oscillation) Clock frequency (High speed, PLL used) Clock frequency (High speed, 1/2 division input) Clock cycle time Frequency regulation (when locked) Input clock pulse width Input clock rise and fall time CPU Internal operation system clock frequency Peripheral system CPU Internal operation system clock cycle time Peripheral system
Value Min 10 Max 25
Unit
Remarks Self oscillation allowable range PLL-use allowable area for self oscillation and external clock input *1 External clock input allowable range
MHz
fC
10
25
MHz
10 tC f PWH, PWL tCR tCF fCP fCPP tCP tLCPP 40 40 40 9.5 0.625 *3 0.625 *3
25 100 10 8 25 25 1600 *3 1600 *3
MHz ns % ns ns MHz MHz ns ns
*2
(tCR + tCF)
*1 : Although PLL allows selection among x1 and x2 multiplication modes, the selection is limited by oscillation frequency as follows: Specifying "x2 multiplication" is not allowed if oscillation frequency exceeds 12.5 MHz. *2 : Frequency regulation indicates a maximum fluctuation from a specified center frequency under locked frequency multiplication.
f =
fO
+ x 100 (%) fO -
29
MB91F127/F128
*3 : This is a value in the case where 10 MHz signal, a minimum value of clock frequency, is input to X0 and where 1/2-division in oscillation circuit and 1/8-gear are used.
tC 0.8 VCC 0.2 VCC PWH tcf PWL tcr
Source voltage (V) Operation-guaranteed area (TA = -30 C to +70 C)
3.6
3.0
25
Frequency (MHz)
30
MB91F127/F128
(2) Clock Output Timing
(VCC = 3.3 V 0.3 V, AVSS = VSS = 0 V, TA = -30 C to +70 C) Pin name CLK CLK CLK Condition Value Min tCP Max Unit ns ns ns Remarks *1 *2 *3
Parameter Cycle time CLK CLK CLK CLK
Symbol tCYC tCHCL tCLCH
1 / 2 x tCYC - 10 1 / 2 x tCYC + 10 1 / 2 x tCYC - 10 1 / 2 x tCYC + 10
*1 : tCYC is a frequency of 1 clock cycle indicating gear cycle. *2 : The values indicate specifications where x1 gear cycle is used. If gear cycle of 1/2, 1/4, or 1/8 is specified, calculate in the formula below by substituting 1/2, 1/4, or 1/8 into n. Min : (1 - n / 2) x tCYC - 10 Max : (1 - n / 2) x tCYC + 10 *3 : The values indicate specifications where x1 gear cycle is used. If gear cycle of 1/2, 1/4, or 1/8 is specified, calculate in the formula below by substituting 1/2, 1/4, or 1/8 into n. Min : n / 2 x tCYC - 10 Max : n / 2 x tCYC + 10 Clock output timing
tCYC tCHCL VOH tcLCH VOH VOL
CLK
(3) Reset Input Ratings
(VCC = 3.3 V 0.3 V, AVSS = VSS = 0 V, TA = -30 C to +70 C) Pin name RST Condition Value Min tCP x 5 Max Unit ns Remarks
Parameter Reset input time
Symbol tRSTL
tRSTL
RST
0.2 VCC
31
MB91F127/F128
(4) Power-on Reset (VCC = 3.3 V 0.3 V, VSS = 0 V, TA = -30 C to +70 C) Parameter Power supply rise time Power supply shut off time Oscillation stabilizing wait time Symbol Pin name VCC Condition Value Min 2 2 x tC x 221 + 100 s Max 20 Unit Remarks VCC < 0.2 V before turning on power
tR
VCC = 3.3 V
ms
tOFF tOSC
VCC
ms ns
tR
VCC
0.9 VCC 0.2 V tOFF
A sudden change of supply voltage may activate the power-on reset function. It is recommended that power voltage should be changed smoothly with less fluctuation of voltages.
3.3 V VCC 2.0 V
Retaining RAM data
VSS
The rising slope is recommended to be less than 50 mV / ms.
VCC RST
tOSC
tRSTL
Be sure to turn on the power while keeping RST terminal at L level first. When the power becomes VCC level, rise the voltage to H level after a period of tRSTL.
32
MB91F127/F128
(5) Normal Bus Access Read/Write Operation
(VCC = 3.3 V 0.3 V, VSS = 0 V, TA = -30 C to +70 C) Value Min Max 15 15 15 15 15 15 15 15 3 / 2 x tcyc - 25 tcyc - 25 Unit ns ns ns ns ns ns ns ns ns ns ns ns *1 *2 *1 Remarks
Parameter CS0 to CS5 delay time CS0 to CS5 delay time Address delay time Data delay time RD delay time RD delay time WR0, 1 delay time WR0, 1 delay time Valid address Valid data input time RD Valid data input time Data setup RD Time RD Data hold time
Symbol tCHCSL tCHCSH tCHAV tCHDV tCLRL tCLRH tCLWL tCLWH tAVDV tRLDV tDSRH tRHDX
Pin name
Condition
CLK CS0 to CS5 CLK A24 to A00 CLK D31 to D16 CLK RD CLK WR0, 1 A24 to A00 D31 to D16
RD D31 to D16
25 0
*1 : If the bus is expanded by automatic wait insertion or RDY input, add time (tcyc x the number of expanded cycles) to the rated value. *2 : The ratings are based on conditions with "gear cycle x 1". If gear cycle of 1/2, 1/4, or 1/8 is specified, calculate in the formula below by substituting 1/2, 1/4, or 1/8 into n. Formula : (2 - n / 2) x tCYC - 25
33
MB91F127/F128
tCYC 2.4 V 0.8 V tCHCSL 2.4 V 0.8 V tCHCSH 2.4 V 2.4 V
CLK
CS0 ~ CS5
tCHAV
0.8 V
2.4 V
2.4 V 0.8 V tCLRH 2.4 V tRLDV tAVDV tDSRH Read tRHDX 2.4 V 0.8 V
A24 ~ A00
0.8 V tCLRL
RD
D31 ~ D16
CLK
2.4 V 0.8 V tCLWL 0.8 V tCLWH 2.4 V
WR (WR0 ~ WR1)
2.4 V
2.4 V 0.8 V
A24 ~ A00
0.8 V tCHDV 2.4 V
D31 ~ D16
0.8 V
write data
2.4 V 0.8 V
34
MB91F127/F128
(6) Timeshared Bus Access Read/Write Operations
(VCC = 3.3 V 0.3 V, VSS = 0 V, TA = -30 C to +70 C) Value Min Max 10 10 15 15 15 15 10 10 10 10 tCYC - 25 Unit ns ns ns ns ns ns ns ns ns * Remarks
Parameter ALE delay time ALE delay time CS1 delay time CS1 delay time Address delay time Data delay time RD delay time RD delay time WR0, 1 delay time WR0, 1 pulse width RD Valid data input time Data setup RDtime RD Data hold time
Symbol tCLLH2 tCLLL2 tCHCSL2 tCHCSH2 tCHAV2 tCHDV2 tCLRL2 tCLRH2 tCLWL2 tCLWH2 tRLDV2 tDSRH2 tRHDX2
Pin name CLK ALE CLK CS1 CLK D31 to D16 CLK RD CLK WR0 WR1
Condition
RD D31 to D16
25 0
* : If the bus is expanded by automatic wait insertion or RDY input, add time (tcyc x the number of expanded cycles) to the rated value.
35
MB91F127/F128
tCYC MA1 MA1 2.4 V 0.8 V tCLLH2 0.8 V tCLLL2 2.4 V 2.4 V 0.8 V 0.8 V BA1 BA1 2.4 V 2.4 V
CLK
ALE
tCHCSL2
0.8 V tCHCSH2 2.4 V
CS1
0.8 V
D31-D16 Multiplex bus for reading
tRLDV2 2.4 V 0.8 V tCHAV2
tDSRH2
tRHDX2 2.4 V 0.8 V
Address
2.4 V 0.8 V
2.4 V 0.8 V
Read
RD
tCLRL2
2.4 V 0.8 V tCLRH2
D31-D16 Multiplex bus for writing
2.4 V 0.8 V tCHAV2
Address
tCHDV2
2.4 V 0.8 V
Write
WR0 - WR1
tCLWL2
2.4 V 0.8 V tCLWH2
A15-A08 for non-multi
2.4 V 0.8 V tCHAV2
36
MB91F127/F128
(7) Ready Input Timing
(VCC = 3.3 V 0.3 V, AVSS = VSS = 0 V, TA = -30 C to +70 C) Symbol tRDYS tRDYH Pin name RDY CLK CLK RDY Condition Value Min 15 0 ns Max Unit ns Remarks
Parameter RDY setup time RCLK CLK RDY hold time
tCYC
2.4 V
2.4 V 0.8 V 0.8 V
CLK
tRDYS
tRDYH
tRDYS tRDYH
RDY
With waiting
0.8 V
2.4 V
RDY
2.4 V
Without waiting
0.8 V
37
MB91F127/F128
(8) Hold Timing
(VCC = 3.0 V 0.3 V, AVSS = VSS = 0 V, TA = -30 C to +70 C) Symbol tCHBGL tCHBGH tXHAL BGRNT tHAHV tCYC - 10 tCYC + 10 ns Pin name CLK BGRNT Condition Value Min tCYC - 10 Max 10 10 tCYC + 10 Unit ns ns ns Remarks
Parameter BGRNT delay time BGRNT delay time Terminal floating BGRNT time BGRNT Terminal valid time
Note : More than one cycle is required for BGRNT to change after BRQ is input.
tCYC
2.4 V
2.4 V
2.4 V
2.4 V
CLK
BRQ
tCHBGL tCHBGH 2.4 V 0.8 V tXHAL tHAHV
BGRNT
Each pin High-Z
38
MB91F127/F128
(9) UART Timing
(VCC = 3.3 V 0.3 V, VSS = 0 V, TA = -30 C to +70 C) Symbol Pin name tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX tBUSY tCLZO tCLSL tCHOZ External shift clock mode Internal shift clock mode Condition Value Min 8 tCYCP* -10 50 50 4 tCYCP* - 10 4 tCYCP* - 10 0 50 50 50 Max +50 50 6 tCYCP* 50 3 tCYCP* Unit ns ns ns ns ns ns ns ns ns ns ns ns ns Remarks
Parameter Serial clock cycle time SC SO delay time Valid SI SC SC Valid SI hold time Serial clock "H" pulse width Serial clock "L" pulse width SC SO delay time Valid SI SC SC Valid SI hold time Serial busy time CS SC, SO delay time CS SC input mask time SC SC, SO Hi-z time
* : tCYCP is a cycle time of peripheral system clock. Internal shift clock mode
tSCYC
SC
tSLOV
SO SI
tIVSH tSHIX
External shift clock mode
tCLZO tSLSH tSHSL tBUSY tCHOZ
SC
tSLOV
SO SI
tIVSH tSHIX
CS
tCLSL
39
MB91F127/F128
(10) Trigger Input Timing
(VCC = 3.3 V 0.3 V, VSS = 0 V, TA = -30 C to +70 C) Symbol tTRGH tTRGL Pin name ATG, INT0, 1, 2, 3 INT4, 5 Condition Value Min 5 tCYCP* Max Unit Remarks
Parameter
Input pulse width
ns
* : tCYCP is a cycle time of peripheral system clock.
ATG INT0, 1, 2, 3 INT4, 5
tTRGH
tTRGL
40
MB91F127/F128
(11) A/D Converter Block Electrical Characteristics (VCC = 3.3 V 0.3 V, AVSS = VSS = 0 V, TA = -30 C to +70 C) Parameter Resolution Total error Linearity error Differential linearity error Zero transition voltage Full-scale transition voltage Conversion time Analog input current Analog input voltage Reference voltage Power supply current Reference voltage supply current Variation among channels Symbol V0t VFST IAIN VAIN IA IAH IR IRH Pin name AN0 to AN7 AN0 to AN7 AN0 to AN7 AN0 to AN7 AVRH AVCC AVRH AN0 to AN7 Value Min AVSS - 1.5 LSB AVRH - 5.5 LSB 5.3 AVSS AVSS Typ 10 AVSS + 0.5 LSB AVRH - 1.5 LSB 0.1 3.0 100 Max 10 4.0 3.5 2.0 AVSS + 2.5 LSB AVRH + 0.5 LSB 10 AVRH AVCC 5.0 5.0 150 10 4 Unit BIT LSB LSB LSB mV mV s A V V mA A A A LSB Remarks
Notes : * Relatively, the errors increase as |AVRH| value becomes smaller. * Define an output impedance of external circuit analog input under the following conditions : Output impedance of external circuit 2 (k) If an output impedance of external circuit is exceedingly high, sampling time for analog voltage may run short.
41
MB91F127/F128
Analog input circuit model diagram
Cin = Approx 30 pF Rin Analog input Comparator Approx. 3.6 k Comparator AVRH Be switched on, only while A/D conversion is performed.
Comparator
Note : Use the values shows as guides only. AVSS/ AVRL
42
MB91F127/F128
5. A/D Converter Block Electrical Characteristics
* Resolution Analog variations recognized by an A/D converter. * Linearity error Deviation of actual conversion characteristics from an ideal line, which is across zero-transition point ("00 0000 0000" "00 0000 0001") and full-scale transition point ("11 1111 1110" "11 1111 1111") * Differential linearity error Deviation from ideal value of input voltage, which is required for changing output code by 1 LSB. * Total error Difference between actual value and ideal value. The error includes zero-transition error, full-scale transition error, and linearity error.
Total error
3FF 3FE 3FD
Actual characteristics
{1 LSB' ( N - 1 ) + 0.5 LSB'}
1.5 LSB'
Digital output
004 003 002 001 0.5 LSB' AVSS
VNT
(Actual measured value)
Actual characteristics Ideal characteristics
Analog input
AVRH
1 LSB' (Ideal value) =
AVRH - AVSS 1024
[V]
Total error of digital output N =
VNT - {1 LSB' x (N - 1) + 0.5 LSB'} 1 LSB'
VNT : Transition voltage for digital output to change from (N+1) to N. VOT' (Ideal value) = AVSS + 0.5 LSB'
[V]
VFST' (Ideal value) = AVRH - 1.5 LSB' [V]
(Continued)
43
MB91F127/F128
(Continued)
Linearity error
3FF 3FE {1 LSB' ( N - 1 ) + VOT} 3FD
Differential linearity error Actual conversion characteristics
N+1
Actual conversion characteristics
VFST (Actual measured value)
Digital output
Digital output
N
Ideal characteristics
004 003 002 001
VNT (Actual measured value)
N-1
Actual conversion characteristics Ideal characteristics
N-2
(Actual measured value) VNT (Actual measured value)
VFST
VOT (Actual measured value)
AVSS
Actual conversion characteristics Analog input
AVRH
Analog input
AVRH
AVSS
Linearity error of digital output N =
VNT - {1 LSB' x (N - 1) + VOT} 1 LSB' V (N + 1) T - VNT} 1 LSB' -1
[LSB] [LSB]
Differential linearity error of digital output N = 1 LSB = VFST - VOT 1022
[V]
VOT : Transition voltage for digital output to change from (000)H to (001)H. VFST : Transition voltage for digital output to change from (3FE)H to (3FF)H.
44
MB91F127/F128
s FLASH MEMORY WRITE/ERASE CHARACTERISTICS
Parameter Sector erase time Chip erase time Half byte (16 bit width) writing time Write/erase cycle Data holding time TA = +25 C, VCC = 3.3 V Condition Value Min Typ 1 4 16 10,000 100,000 Max 15 3600 Unit s s s cycle h Remarks Not including time for internal writing before deletion. Not including time for internal writing before deletion. Not including system-level overhead time.
45
MB91F127/F128
s EXAMPLE CHARACTERISTICS
* Power Supply Current Power Supply Current vs. Power Supply Voltage
80 70 fc = 25 MHz
Power Supply Current (sleeping) vs. Power Supply Voltage
60 50 fc = 25 MHz
ICCS (mA)
3 3.3 3.6 3.9
60
ICC (mA)
50 40 30 20 10 0 2.7
40 30 20 10 0 2.7 3 3.3 3.6 3.9
VCC (V)
VCC (V)
Power Supply Current (stopping) vs. Power Supply Voltage
100 90 80 70 60 50 40 30 20 10 0 -10 2.7 fc = 25 MHz
A/D Power Supply Current vs. Power Supply Voltage
10 9 8 7 6 5 4 3 2 1 0 -1 2.7 fc = 25 MHz
ICCH (A)
IA (mA)
3
3.3
3.6
3.9
3
3.3
3.6
3.9
VCC (V)
VCC (V)
A/D Reference Power Supply Current vs. Power Supply Voltage
180 160 140 120 100 80 60 40 20 0 2.7 fc = 25 MHz
IR (A)
3
3.3
3.6
3.9
VCC (V)
46
MB91F127/F128
* Output Voltage "H" Output Voltage vs. Power Supply Voltage
4 3.8 3.6 3.4 3.2 3 2.8 2.6 2.4 2.2 2 2.7 300 270
"L" Output Voltage vs. Power Supply Voltage
VOL (mV)
VOH (V)
240 210 180 150 2.7 3 3.3 3.6 3.9
3
3.3
3.6
3.9
VCC (V)
VCC (V)
Pull-up resistance vs. Power Supply Voltage
100
R (k)
10 2.7
3
3.3
3.6
3.9
VCC (V)
47
MB91F127/F128
s ORDERING INFORMATION
Part number MB91F127PFV MB91F128PFV Package 100-pin plastic LQFP (FPT-100P-M05) 100-pin plastic LQFP (FPT-100P-M05) Remarks
48
MB91F127/F128
s PACKAGE DIMENSIONS
100-pin plastic LQFP (FPT-100P-M05)
16.000.20(.630.008)SQ 14.000.10(.551.004)SQ
75 51
*Pins width and pins thickness include plating thickness.
76
50
0.08(.003) Details of "A" part
INDEX
1.50 -0.10 .059 -.004 (Mounting height)
26
+0.20
+.008
100
0.100.10 (.004.004) (Stand off) 0.25(.010)
0~8 "A" 0.500.20 (.020.008) 0.600.15 (.024.006)
1
25
0.50(.020)
0.200.05 (.008.002)
0.08(.003)
M
0.1450.055 (.0057.0022)
C
2000 FUJITSU LIMITED F100007S-3c-5
Dimensions in mm (inches)
49
MB91F127/F128
FUJITSU LIMITED
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., submersible repeater and artificial satellite). Please note that Fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
F0201 (c) FUJITSU LIMITED Printed in Japan

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